1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus, capable of reducing the precharge time of local input/output lines LIO.
2. Related Art
Due to the recent increase in the density of high-speed dynamic random access memories (DRAM), there have been limitations to the package size used in a plurality of product groups (e.g., mobile and graphic product groups). In order to overcome the limitations, the structure of the DRAM has been implemented in various forms. One of the structures, which have recently been used for high-speed and high-density DRAMs, is a structure in which banks are combined in the direction that a row address increases so as to form one bank.
Hereinafter, a conventional semiconductor memory apparatus will be described with reference to FIGS. 1 and 2.
Referring to FIG. 1, a conventional semiconductor memory apparatus includes a first sub bank 110, a second sub bank 130, a first precharge section 150, a second precharge section 170 and a center bitline sense amplifier array 190.
The first precharge section 150 is arranged above the first sub bank 110 and precharges local input/output lines LIO of the first sub bank 110 and the second sub bank 130. The second precharge section 170 is arranged below the second sub bank 130 and precharges the local input/output lines LIO of the first sub bank 110 and the second sub bank 130. The center bitline sense amplifier array 190 is arranged in the area where the first sub bank 110 and the second sub bank 130 are connected each other.
The first sub bank 110 is arranged above the center bitline sense amplifier array 190. The second sub bank 130 is arranged below the center bitline sense amplifier array 190.
The first precharge section 150 includes a plurality of precharge control sections 150-1 to 150-N.
The second precharge section 170 includes a plurality of precharge control sections 170-1 to 170-N.
Generally, cell data selected by an external address is amplified by a bitline sense amplifier (BLSA). The amplified data is output to an input/output terminal by a column decoder through a global input/output line GIO.
Generally, the semiconductor memory has a bank structure including the first sub bank 110 and the second sub bank 130. The first sub bank 110 and the second sub bank 130 are connected in the direction in which the row address increases. A word line WL is simultaneously activated in the first sub bank 110 and the second sub bank 130. Due to the bank structure, there is an increase in the length of the local input/output line LIO(UP) arranged in the direction in which the row address increases. Therefore, there is a problem in that the time to precharge local input/output lines LIO(UP) and LIO(DOWN) by means of the plurality of precharge control sections 150-1 to 150-N and the plurality of precharge control sections 170-1 to 170-N increases.
Referring to FIG. 2, when a read command READ or a write command WRITE is applied, a corresponding column address selection signal YI is enable. When the column address selection signal YI is enabled, data is input to or output from the bitline sense amplifier (BLSA) through the local input/output lines LIO. When a precharge signal LIO_PCG is at a logic high level, the local input/output lines LIO are precharged.
If the local input/output line LIO becomes long, the load of the local input/output lines LIO increases due to high resistance or capacitance, resulting in slow precharging. Therefore, potential regions A, A-1, B, and B-1, where the local input/output lines LIO are precharged to a precharge voltage level Vpcg, are temporarily delayed. Accordingly, CAS to CAS command delay (tCCD) or internal WRITE to READ command delay (tWTR), which are characteristic to a DRAM, may deteriorate, thereby causing high speed operations to fail or operations which do not follow a predetermined specification to be performed.
Further, if a read operation is performed when local input/output line LIO is not sufficiently precharged, erroneous data may be amplified in the input/output sense amplifier, which causes the DRAM operation to fail. Therefore, after the read operation or the write operation is performed, the local input/output line LIO should be precharged as soon as possible to ensure stable DRAM operation.